1. Field of the Invention
The present invention relates to a communication device provided with a multiple bus having plural channels via each of which a signal is transmitted and plural modules for sending/receiving a signal via the multiple bus, a multiple bus control device for arbitrating requests for communication between the plural modules via the multiple bus and an LSI for controlling the multiple bus in which the multiple bus control device is realized.
2. Description of the Related Art
Recently, a data processing rate by LSI has been rapidly accelerated by the progress of semiconductor integration technology. As the data processing rate is accelerated, the enhancement of signal transmission ability is demanded for a wiring board packaging a semiconductor integrated circuit.
Particularly in recent years, so-called parallel processing architecture provided with plural high speed CPU chips is adopted in a server-type system equivalent to a high-order device of a personal computer. The classification of the parallel processing architecture is described on pages 6 to 13 of xe2x80x9cParallel computersxe2x80x9d written by DR. Hideharu Amano and published by Shokodo for example. According to this book, if a system is composed of plural modules for executing data processing such as CPU, a method of connecting modules is classified into a type of connection via a bus, a type of connection via a switch and a type of connection via a network. Of these, the type of connection via a bus is not suitable for the connection of multiple modules, however, the type has a merit that the structure is simple, compared with other types, the quantity of hardware is small and the type is excellent in expandability. The type of connection via a bus is widely used in a commercial computer including a personal computer and computer application products.
In connection via a bus, communication performance proportional to the processing rate and the number of connected modules is demanded. Many multiple bus systems each of which enables enhancing communication performance by multiplexing a bus itself are proposed. In the case of a parallel processing system, as plural modules can access to each bus, means to solve access contention is required. For the above means, for example, Japanese Published Unexamined Patent Application No. Hei 5-282242 is disclosed. In the above application, an bus arbiter that arbitrates access contention is provided and each bus master outputs a request for transmission to the bus arbiter. In the meantime, the bus arbiter first retrieves an idle bus signal line, determines a bus master which is permitted to use the bus signal line and sends a signal showing that the use of the bus signal line is permitted or unpermitted to each bus master.
A concrete example of the configuration of a bus arbiter in a multiple bus system is described on pages 295 to 297 of the second edition xe2x80x9cComputer Architecture Design and Performancexe2x80x9d written by B. Wilkinson, translated by Yoshizo Takahashi and published by Prentise Hall/Toppan for example. Referring to FIG. 1, the configuration of a bus arbiter will be described below.
FIG. 1 shows an example of a conventional type multiple bus control device.
In a multiple bus, there occur not only bus contention but access contention to a communication destination such as a memory. To solve the above problem, an arbiter having two steps as shown in FIG. 1 is provided. A first step is an arbiter provided to a communication destination (memory arbiters 301a and 301b in this example) and hereby, it is determined that one of plural CPUs 303a, . . . , 303z has an access right to access to each memory 302a and 302b. The memory arbiters are required by the number of memories. A second step is a normal bus arbiter 304 and the bus arbiter 304 gives a right to use a bus not to CPU but to the output of each memory arbiter 301a and 301b. Finally, CPU having a right to use each memory and each bus is determined.
As multiple connectors and wiring are required when modules in a parallel processing system are connected, wiring has been multilayered and micronized to enhance communication performance and the density of wiring. However, the multilayering and micronization of wiring are approaching a limit because of the delay of a signal and the distortion of a transmitted waveform caused by capacity between wiring and the resistance of wiring. Electromagnetic interference (EMI) caused by accelerating operating speed is also a serious problem.
As described above, the throughput of a data processor is often limited by the transmission capability of a bus on a wiring board. Then, it is examined to overcome the limit of an electric bus that in-system optical connection technology called optical interconnection is used. For optical interconnection technology, various embodiments are proposed depending upon the contents of the configuration of a system as disclosed on pages 201 and 202 of a lecture by Mr. Uchida in the ninth Circuit Mounting Lecture Meeting 15C01, on pages 81 to 86 of xe2x80x9cPackaging Technology for Optical Interconnectsxe2x80x9d, IEEE Tokyo 1994, No. 33 by Mr. H. Tomimuro et al. and on pages 52 to 55 of xe2x80x9cElectronicsxe2x80x9d the April number written by Mr. Wada and published in 1993. The optical interconnection technology has merits that high frequency operation exceeding that in electric interconnection technology is enabled, moreover electromagnetic interference can be reduced, transmission bandwidth can be expanded by multiplexing using wavelength, amplitude and others, and simultaneous two-way communication is enabled.
Particularly, as spatial optical transmission technology enables simultaneous communication among multiple ports and does not require the physical connection of bus signal lines, it is matched with the above multiple bus system. Technology similar to the above technology is disclosed in Japanese Published Unexamined Patent Application No. Hei 4-305757 for example. The above application relates to technology for connecting plural modules such as CPU, a memory and an I/O device not by spatial optical transmission but by radio transmission and radio transmission has merits that simultaneous communication among multiple ports is enabled and the physical connection of bus signal lines is not required similarly to spatial optical transmission, compared with an electric bus. The technology disclosed in Japanese Published Unexamined Patent Application No. Hei 4-305757 relates to a system for implementing communication among modules according to a spread spectrum system and a bus arbiter is provided with a function for connecting arbitrary two modules.
Similarly, technology for implementing simultaneous broadcast communication among multiple ports by spatial optical transmission is disclosed in Japanese Published Unexamined Patent Application No. Hei 10-123374. The above technology realizes optical communication between ports installed on the end face of a flat optical waveguide and realizes a broadcast by branching incident signal light by refracting it and transmitting it on the opposite end face.
FIG. 2 is a schematic drawing showing a state of the transmission of an optical signal provided with a directional propagation property.
As shown in FIG. 2, an optical signal is provided with a directional propagation property and incident light is transmitted only to a port on the opposite end face. FIG. 3 equivalently represents the above state by an electric circuit. A simultaneous communication function in reverse directions is implemented owing to a directional propagation property by setting different channels to reverse directions using the same wavelength, the same communication zone and others which enable only setting one channel in case a two-way propagation property.
In such a conventional type multiple bus system as disclosed in the above Japanese Published Unexamined Patent Application No. Hei 5-282242, multiplexing one-to-one communication between modules or access control to implement broadcast communication is executed. However, in multitask environment in which each module executes an independent task, a communication function that can correspond to further diverse combination is required. Referring to FIG. 4, the above example will be described below. FIG. 4 shows examples of communication variations acquired by combining each address signal line (a full line) and each data signal line (a dotted line) among two CPUs and two memory modules. The following communication variations (1) to (5) are conceivable.
(1) A parallel access by one-to-one communication (FIG. 4A)
(2) Simultaneous writing from one CPU to plural memories by multicast (=one-to-multiple) communication via an address signal line and a data signal line (FIG. 4B)
(3) Only an address is multicast from one CPU and data is accessed in parallel by one-to-one communication. (FIG. 4C)
(4) Only an address is sent from one CPU to one memory and read data is multicast to plural CPUs. (FIG. 4D)
(5) Only an address is sent from each CPU to each memory by one-to-one communication and data is simultaneously written from a specific one CPU to plural memories. (FIG. 4E)
The above (1) to (5) may be also simultaneously required.
To implement access control by which buses are possibly always used to meet these requests, the contention of accesses to a transmission channel and the contention of accesses to a communication destination are required to be simultaneously solved as described above. Particularly, to implement an efficient pipeline access in which address sending from CPU and a data response from a memory can be simultaneously executed in case information is read from a high speed memory to which a pipeline access is enabled, each transmission channel is required to be allocated beforehand so that a sending destination of an address and a response destination of data do not contend with another access.
However, in the above Japanese Published Unexamined Patent Application No. Hei 5-282242, means to solve the contention of accesses to a communication destination is not provided. For example, if a communication partner module is busy, a module that requests communication is required to wait until the partner becomes free and a bus is idle. To prevent such a situation, a distributed transaction method is proposed. According to this method, if a partner module is busy, then communication is once interrupted, a bus signal line is released and after the partner becomes free, processing is started from the arbitration of buses again. However, in this method, the partner is also required to request a bus, an interface circuit to be a bus master is also required to be added to a module such as a memory and there is a problem that the scale of hardware is increased.
In the meantime, a method of the above arbitration shown in FIG. 1 corresponds to problems of both access contention at a communication destination and bus contention. However, as each memory arbiter independently determines an access right to each memory, an access right to plural memories as in multicast communication cannot be acquired.
In the above Japanese Published Unexamined Patent Application No. Hei 4-305757, communication between modules is limited to one-to-one communication and the above (2) to (5) cannot be implemented. A method of concretely implementing access control such as a request for communication and arbitration is not clarified.
Further, in a transmitter depending upon a signal provided with a directional propagation property such as disclosed in the above Japanese Published Unexamined Patent Application No. Hei 10-123374, an availability factor is enhanced by allocating a channel for every direction. In communication among CPUs and memory modules shown in the above (1) to (5), writing to a memory can be implemented by only a channel in a direction from CPU to a memory and a channel in a reverse direction from the memory to CPU can be utilized for other communication. However, there is a problem that in a conventional type multiple bus control device, a function to arbitrate channels independently for every propagational direction and to avoid the contention of accesses to a destination in each propagational direction cannot be implemented.
Further, to detect the contention of accesses to a destination in a sending direction to solve the above problems, an address of an access destination is required to be acquired when communication is requested. In a conventional type bus system, a bus can be requested by one bit per port, however, further, an address of a sending destination and an address signal of a response destination are required. In addition, if the simultaneous specification of arbitrary plural destinations is enabled as in a multicast, the quantity of signals is further increased. As a result, when access control is implemented by an LSI chip, there is a problem that pins to input a communication request signal from each port are remarkably increased.
The present invention is made to solve the above various problems and implements various communication among modules and to provide a multiple bus control device which can also be applied to access control by a signal having a directional propagation property, an LSI for controlling the multiple bus in which the multiple bus control device is realized and a communication device for implementing various communication among modules.
A communication device according to the present invention is provided with a multiple bus provided with plural channels over each of which a signal is transmitted, plural modules for sending/receiving a signal via the multiple bus and an arbiter for arbitrating a right to use the multiple bus among the plural modules and is characterized in that each of the above plural modules requests communication to the arbiter by sending communication request information for specifying one or more communication partner modules to the arbiter when the above module that requests communication communicates with another one or more modules and in that the above arbiter specifies an idle channel based upon received communication request information in case a communication partner specified in the communication request information is in an idle state in which new communication is possible and an idle channel over which new communication is possible exists in the above multiple bus and permits communication using the specified idle channel between a module which sends the communication request information and a module which is a communication partner specified in the communication request information.
In the multiple bus control device, a communication request receiving unit is provided for receiving a request for communication from each module by receiving communication request information for specifying one or more communication partner modules from each of plural modules for sending/receiving a signal utilizing a multiple bus provided with plural channels over each of which a signal is transmitted, and an arbiter is provided for outputting information for specifying an idle channel and information for specifying plural modules for which communication using the specified idle channel is permitted based upon communication request information received by the communication request receiving unit in case a communication partner specified in the communication request information is in an idle state in which new communication is possible and an idle channel over which new communication is possible exists.
Further, an LSI for controlling a multiple bus according to the present invention is provided with a storage for storing a table describing correspondence between each of plural modules for sending/receiving a signal using a multiple bus provided with plural channels over each of which a signal is transmitted and one or more communication partner modules specified in a request for communication from each module, an input terminal for inputting a communication request signal including information for specifying one correspondence in the above correspondence table from each of the above plural modules, a register for storing information included in the communication request signal input from the above input terminal, an arbiter for generating information for specifying an idle channel and information for specifying plural modules for which communication using the specified idle channel is permitted based upon correspondence in the above correspondence table specified based upon the information stored in the above register in case a communication partner specified based upon the correspondence is in an idle state in which new communication is possible and an idle channel over which new communication is possible exists, and an output terminal for outputting an arbitration signal showing the information generated by the arbiter.